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cy14c064pa cy14b064pa cy14e064pa 64kbit (8 k 8) spi nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 951341709 ? 4089432600 document #: 00168249 rev. *a revised may 6, 2011 64-kbit (8 k 8) spi nvsram with real time clock features 64kbit nonvolatile static random access memory (nv sram) internally organized as 8 k 8 store to quantumtrap nonvolatile elements initiated automatically on powerdown (autostore) or by using spi instruction (software store) or hsb pin (hardware store) recall to sram initiated on powerup (power up recall) or by spi instruction (software recall) automatic store on powerdown with a small capacitor high reliability infinite read, write, and recall cycles 1 million store cycles to quantumtrap data retention: 20 years at 85 c real time clock (rtc) fullfeatured rtc watchdog timer clock alarm with programmable interrupts backup power fail indication square wave output with programmable frequency (1 h z, 512 hz, 4096 hz, 32.768 khz) capacitor or battery backup for rtc backup current of 0.45 a (typical) 40 mhz, and 104 mhz highspeed serial peripheral in terface (spi) 40 mhz clock rate spi write and read with zero cycl e delay 104 mhz clock rate spi write and read (with special fast read instructions) supports spi mode 0 (0,0) and mode 3 (1,1) spi access to special functions nonvolatile store/recall 8byte serial number manufacturer id and product id sleep mode write protection hardware protection using write protect (wp ) pin software protection using write disable instruction software block protection for 1/4, 1/2, or entire a rray low power consumption average active current of 3 ma at 40 mhz operation average standby mode current of 250 a sleep mode current of 8 a industry standard configurations operating voltages: ? cy14c064pa : v cc = 2.4 v to 2.6 v ? cy14b064pa : v cc = 2.7 v to 3.6 v ? cy14e064pa : v cc = 4.5 v to 5.5 v industrial temperature 16pin small outline integrated circuit (soic) pack age restriction of hazardous substances (rohs) complian t overview the cypress cy14x064pa combines a 64 kbit nvsram [1] with a fullfeatured rtc in a monolithic integrated circ uit with serial spi interface. the memory is organized as 8 k words of 8 bits each. the embedded nonvolatile elements incorporate the quantumtrap technology, creating the worlds most r eliable nonvolatile memory. the sram provides infinite read and write cycles, while the quantumtrap cells provide highly reliable nonvolatile storage of data. data transfers from sr am to the nonvolatile elements (store operation) takes place automatically at powerdown. on powerup, data is r estored to the sram from the nonvolatile memory (recall operat ion). you can also initiate the store and recall operatio ns through spi instruction. note 1. this device will be referred to as nvsram through out the document. memory data & address control manufacture id/ product id spi control logic write protection instruction decoder power control block rdsn/wrsn/rdid serial number 8 x 8 quantrumtrap 8 k x 8 sram 8 k x 8 store si cs sck wp v cc v cap recall rtc control logic registers counters int/sqw x in x out v rtccap read/write status register wrsr/rdsr/wren store/recall/asenb/asdisb rdrtc/wrtc v rtcbat so sleep logic block diagram [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 2 of 43 contents pinout ............................................ .................................... 3 pin definitions ................................... ............................... 3 device operation .................................. ............................ 4 sram write ........................................ ......................... 4 sram read ......................................... ....................... 4 store operation ................................... .................... 4 autostore operation ............................... ..................... 4 software store operation .......................... .............. 5 hardware store and hsb pin operation .............. ... 5 recall operation .................................. .................... 5 hardware recall (power up) ........................ ........... 5 software recall ................................... .................... 5 disabling and enabling autostore .................. ............. 5 serial peripheral interface ....................... ........................ 6 spi overview ...................................... ......................... 6 spi modes ......................................... ................................ 7 spi operating features ............................ ........................ 8 powerup .......................................... .......................... 8 poweron reset .................................... ...................... 8 power down ........................................ ........................ 8 active power and standby power modes .............. ..... 8 spi functional description ........................ ...................... 9 status register ................................... ............................ 10 read status register (rdsr) instruction ........... ...... 10 fast read status register (fast_rdsr) instruction ....................................... .................................. 10 write status register (wrsr) instruction .......... ...... 10 write protection and block protection ............. ............ 11 write enable (wren) instruction ................... ........... 11 write disable (wrdi) instruction .................. ............ 12 block protection .................................. ...................... 12 hardware write protection (wp pin) ................ ......... 12 memory access ..................................... ......................... 12 read sequence (read) instruction .................. ........ 12 fast read sequence (fast_read) instruction ...... 12 write sequence (write) instruction ................ ........ 13 rtc access ........................................ ............................. 15 read rtc (rdrtc) instruction ...................... ........ 15 fast read sequence (fast_rdrtc) instruction .... 15 write rtc (wrtc) instruction ...................... ......... 16 nvsram special instructions ....................... ................. 17 software store (store) instruction ................ ..... 17 software recall (recall) instruction .............. .... 17 autostore enable (asenb) instruction .............. ....... 17 autostore disable (asdisb) instruction ............ ....... 17 special instructions .............................. ......................... 17 sleep instruction ................................. .................... 17 serial number ..................................... ............................ 18 wrsn (serial number write) instruction ............ ...... 18 rdsn (serial number read) instruction ............. ...... 19 fast_rdsn (fast serial number read) instruction ....................................... .................................. 19 device id ......................................... ................................ 20 rdid (device id read) instruction ................. .......... 20 fast_rdid (fast device id read) instruction ....... . 21 hold pin operation ................................ ................. 21 real time clock operation ......................... ................... 22 nvtime operation .................................. ................... 22 clock operations .................................. ..................... 22 reading the clock ................................. .................... 22 setting the clock ................................. ...................... 22 backup power ...................................... ..................... 22 stopping and starting the oscillator .............. ............ 22 calibrating the clock ............................. .................... 23 alarm ............................................. ............................ 23 watchdog timer .................................... .................... 23 programmable square wave generator ................ ... 24 power monitor ..................................... ...................... 24 backup power monitor .............................. ................ 24 interrupts ........................................ ........................... 24 interrupt register ................................ ....................... 24 flags register .................................... ....................... 25 best practices .................................... ............................. 31 maximum ratings ................................... ........................ 32 dc electrical characteristics ..................... ................... 32 data retention and endurance ...................... ............... 33 capacitance ....................................... ............................. 33 thermal resistance ................................ ........................ 33 ac test conditions ................................ ........................ 34 rtc characteristics ............................... ........................ 35 ac switching characteristics ...................... ................. 35 autostore or power-up recall ...................... ............ 37 switching waveforms ............................... ..................... 37 software controlled store/recall cycles ........... ... 38 hardware store cycle .............................. ................... 39 ordering information .............................. ........................ 40 ordering code definitions ......................... ................ 40 package diagram ................................... ......................... 41 acronyms .......................................... .............................. 42 document conventions .............................. ................... 42 units of measure .................................. ..................... 42 document history page ............................. .................... 43 sales, solutions, and legal information ........... ........... 43 worldwide sales and design support ................ ....... 43 products .......................................... .......................... 43 psoc solutions .................................... ..................... 43 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 3 of 43 pinout figure 1. pin diagram - 16-pin soic pin definitions pin name i/o type description cs input chip select: activates the device when pulled low. driving this pin high puts the device in low power standby mode. sck input serial clock: runs at speeds up to a maximu m of f sck . serial input is latched at the rising edge of this clock. serial output is driven at the falling edge of the clock. si input serial input: pin for input of all spi instr uctions and data. so output serial output: pin for output of data throu gh spi. wp input write protect: implements hardware write prote ction in spi. hold input hold pin: suspends serial operation. hsb input/output hardware store busy: output: indicates busy status of nvsram when low. after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak intern al pullup resistor keeps this pin high (external pullup resistor connection optional). input: hardware store implemented by pulling this p in low externally. v cap power supply autostore capacitor. supplies power to the nvsram during power loss to store data from the sram to nonvolatile elements. if autostore is not n eeded, this pin must be left as no connect. it must never be connected to ground. v rtccap power supply capacitor backup for rtc: left unconnec ted if v rtcbat is used. v rtcbat power supply battery backup for rtc: left unconnecte d if v rtccap is used. xout output crystal output connection xin input crystal input connection int/sqw output interrupt output/calibration/square wave. pro grammable to respond to the clock alarm, the watchdog timer, and the power monitor. also program mable to either active high (push or pull) or low (open drain). in calibration mode, a 512 hz squ are wave is driven out. in the square wave mode, you may select a frequency of 1 hz, 512 hz, 4 ,096 hz, or 32,768 hz to be used as a continuous output. nc no connect no connect. this pin is not connected t o the die. v ss power supply ground v cc power supply power supply int/sqw wp v cap 1 2 34 5 6 7 8 9 10 11 12 13 nc 16 15 14 v cc so si sck cs hsb hold top view not to scale v rtcbat x out x in v rtccap v ss [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 4 of 43 device operation cy14x064pa is a 64kbit serial (spi) nvsram memory with integrated rtc and spi interface. all the reads and writes to nvsram happen to the sram, which gives nvsram the u nique capability to handle infinite writes to the memory. the data in sram is secured by a store sequence that transfers the data in parallel to the nonvolatile quantumtrap cells. a small capacitor (v cap ) is used to autostore the sram data in nonvolatile cells when power goes down providing po werdown data security. the quantumtrap nonvolatile elements built in the reliable sonos technology make nvsram the ideal cho ice for secure data storage. in cy14x064pa, the 64kbit memory array is organize d as 8 k words 8 bits. the memory can be accessed through a standard spi interface that enables very high clock speeds u p to 40 mhz with zero cycle delay read and write cycles. this n vsram chip also supports 104 mhz spi access speed with a speci al instruction for read operation. cy14x064pa supports spi modes 0 and 3 (cpol, cpha = 0, 0 and 1, 1) and oper ates as spi slave. the device is enabled using the chip sel ect (cs ) pin and accessed through serial input (si), serial outp ut (so), and serial clock (sck) pins. cy14x064pa provides the feature for hardware and so ftware write protection through the wp pin and wrdi instruction. cy14x064pa also provides mechanisms for block write protection (1/4, 1/2, or full array) using bp0 and bp1 pins in the status register. further, the hold pin is used to suspend any serial communication without resetting the serial s equence. cy14x064pa uses the standard spi opcodes for memory access. in addition to the general spi instructions for read and write, cy14x064pa provides four special instruction s that allow access to four nvsram specific functions: store, re call, autostore disable (asdisb), and autostore enable (a senb). the major benefit of nvsram over serial eeproms is that all reads and writes to nvsram are performed at the spe ed of spi bus with zero cycle delay. therefore, no wait time is required after any of the memory accesses. the store and rec all operations need finite time to complete and all mem ory accesses are inhibited during this time. while a store or re call operation is in progress, the busy status of the de vice is indicated by the hardware store busy (hsb ) pin and also reflected on the rdy bit of the status register. sram write all writes to nvsram are carried out on the sram an d do not use up any endurance cycles of the nonvolatile memo ry. this allows you to perform infinite write operations. a write cycle is performed through the write instruction. the write instruction is issued through the si pin of the nvs ram and consists of the write opcode, two bytes of address, and one byte of data. write to nvsram is done at spi bus sp eed with zero cycle delay. cy14x064pa allows burst mode writes to be performed through spi. this enables write operations on consecutive a ddresses without issuing a new write instruction. when the l ast address in memory is reached in burst mode, the address rol ls over to 0x0000 and the device continues to write. the spi write cycle sequence is defined in the memo ry access section of spi protocol description. sram read a read cycle is performed at the spi bus speed. the data is read out with zero cycle delay after the read instructio n is executed. read instruction can be used upto 40 mhz clock spee d. the read instruction is issued through the si pin of th e nvsram and consists of the read opcode and two bytes of addres s. the data is read out on the so pin. speed higher than 40 mhz (up to 104 mhz) requires fast_read instruction. the fast_read instruction is issued through the si pin of the nvsram and consists of th e fast_read opcode, two bytes of address, and one dum my byte. the data is read out on the so pin. cy14x064pa enables burst mode reads to be performed through spi. this enables reads on consecutive addr esses without issuing a new read instruction. when the la st address in memory is reached in burst mode read, the addres s rolls over to 0x0000 and the device continues to read. the spi read cycle sequence is defined in the memor y access section of spi protocol description. store operation store operation transfers the data from the sram to the nonvolatile quantumtrap cells. the cy14x064pa store s data to the nonvolatile cells using one of the three sto re operations: autostore, activated on device powerdown; software store, activated by a store instruction; and hardware stor e, activated by the hsb . during the store cycle, an erase of the previous nonvolatile data is first performed, follo wed by a program of the nonvolatile elements. after a store cycle is initiated, read/write to cy14x064pa is inhibited un til the cycle is completed. the hsb signal or the rdy bit in the status register can be monitored by the system to detect if a store or sof tware recall cycle is in progress. the busy status of nvs ram is indicated by hsb being pulled low or rdy bit being set to 1. to avoid unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at lea st one write operation has taken place since the most rece nt store or recall cycle. however, software initiated store cyc les are performed regardless of whether a write operation h as taken place. autostore operation the autostore operation is a unique feature of nvsr am which automatically stores the sram data to quantumtrap c ells during powerdown. this store makes use of an exter nal capacitor (v cap ) and enables the device to safely store the data in the nonvolatile memory when power goes down . during normal operation, the device draws current f rom v cc to charge the capacitor connected to the v cap pin. when the voltage on the v cc pin drops below v switch during powerdown, the device inhibits all memory accesses to nvsram a nd automatically performs a conditional store operatio n using the charge from the v cap capacitor. the autostore operation is not initiated if no write cycle has been performed sinc e last recall. note if a capacitor is not connected to v cap pin, autostore must be disabled by issuing the autostore disable instru ction ( autostore disable (asdisb) instruction on page 17 ). if autostore is enabled without a capacitor on the v cap pin, the device attempts an autostore operation without suff icient charge [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 5 of 43 to complete the store. this will corrupt the data s tored in nvsram, status register as well as the serial numbe r and it will unlock the snl bit. to resume normal functionality, the wrsr instruction must be issued to update the nonvolatil e bits bp0, bp1, and wpen in the status register. figure 2 shows the proper connection of the storage capacit or (v cap ) for autostore operation. refer to dc electrical characteristics on page 32 for the size of the v cap . figure 2. autostore mode software store operation software store allows the user to trigger a store o peration through a special spi instruction. store operation is initiated by executing store instruction regardless of whethe r or not a write has been performed since the last nv operatio n. a store cycle takes t store time to complete, during which all the memory accesses to nvsram are inhibited. the rd y bit of the status register or the hsb pin may be polled to find the ready/busy status of the nvsram. after the t store cycle time is completed, the sram is activated again for read and write operations. hardware store and hsb pin operation the hsb pin in cy14x064pa is used to control and acknowledge store operations. if no store/recall is in progress, this pin can be used to request a hardwar e store cycle. when the hsb pin is driven low, the cy14x064pa conditionally initiates a store operation after t delay duration. a store cycle starts only if a write to the sram ha s been performed since the last store or recall cycle. rea ds and writes to the memory are inhibited for t store duration or as long as hsb pin is low. the hsb pin also acts as an open drain driver (internal 100 k weak pullup resistor) that is internally driven low to indicate a busy condition when the st ore (initiated by any means) is in progress. note after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by an internal 100 k pullup resistor. note for successful last data byte store, a hardware st ore should be initiated at least one clock cycle after the last data bit d0 is received. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. the hsb pin must be left unconnected if not used. recall operation a recall operation transfers the data stored in the nonvolatile quantumtrap elements to the sram. in cy14x064pa, a recall may be initiated in two ways: hardware recal l, initiated on powerup and software recall, initiate d by a spi recall instruction. internally, recall is a two step procedure. first, the sram data is cleared. next, the nonvolatile information is tr ansferred into the sram cells. all memory accesses are inhibited while a recall cycle is in progress. the recall operation does not alter the data in the nonvolatile elements. hardware recall (power up) during powerup, when v cc crosses v switch , an automatic recall sequence is initiated, which transfers the c ontent of nonvolatile memory on to the sram. the data would p reviously have been stored on the nonvolatile memory through a store sequence. a power up recall cycle takes t fa time to complete and the memory access is disabled during this time. hsb pin is used to detect the ready status of the device. software recall software recall allows you to initiate a recall ope ration to restore the content of nonvolatile memory on to the sram. in cy14x064pa, this can be done by issuing a recall in struction in spi. a software recall takes t recall time to complete during which all memory accesses to nvsram are inhibited. the controller must provide sufficient delay for the re call operation to complete before issuing any memory access instru ctions. disabling and enabling autostore if the application does not require the autostore f eature, it can be disabled in cy14x064pa by using the asdisb instr uction. if this is done, the nvsram does not perform a store o peration at powerdown. autostore can be re enabled by using the asenb inst ruction. however, these operations are not nonvolatile and i f you need this setting to survive the power cycle, a store op eration must be performed following autostore disable or enable operation. note cy14x064pa comes from the factory with autostore enabled. if autostore is disabled and v cap is not required, then the v cap pin must be left open. the v cap pin must never be connected to ground. the power up recall operation cannot be disabled in any case. 0.1uf v cc 10kohm v cap cs v cap v ss v cc [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 6 of 43 serial peripheral interface spi overview the spi is a fourpin interface with chip select (c s ), serial input (si), serial output (so), and serial clock (sck) pi ns. cy14x064pa provides serial access to nvsram through spi interface. the spi bus on cy14x064pa can run at spe eds up to 104 mhz except rdrtc and read instruction. the spi is a synchronous serial interface which use s clock and data pins for memory access and supports multiple d evices on the data bus. a device on spi bus is activated usin g the cs pin. the relationship between chip select, clock, and da ta is dictated by the spi mode. cy14x064pa supports spi modes 0 an d 3. in both these modes, data is clocked into the nvsram o n the rising edge of sck starting from the first rising edge aft er cs goes active. the spi protocol is controlled by opcodes. these op codes specify the commands from the bus master to the sla ve device. after cs is activated the first byte transferred from the b us master is the opcode. following the opcode, any add resses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can b e issued. the commonly used terms used in spi protocol are gi ven below: spi master the spi master device controls the operations on a spi bus. a spi bus may have only one master with one or more s lave devices. all the slaves share the same spi bus line s and the master may select any of the slave devices using th e cs pin. all the operations must be initiated by the master acti vating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchronized with this clock. spi slave the spi slave device is activated by the master thr ough the chip select line. a slave device gets the sck as an inpu t from the spi master and all the communication is synchronized wi th this clock. spi slave never initiates a communication on the spi bus and acts on the instruction from the master. cy14x064pa operates as a slave device and may share the spi bus with multiple cy14x064pa devices or other spi d evices. chip select (cs ) for selecting any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. the cy14x064pa is selected when the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a highimpeda nce state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each a ctive chip select cycle. serial clock (sck) serial clock is generated by the spi master and the communication is synchronized with this clock after cs goes low. cy14x064pa allows spi modes 0 and 3 for data communication. in both these modes, the inputs are latched by the slave device on the rising edge of sck and outp uts are issued on the falling edge. therefore, the first ri sing edge of sck signifies the arrival of the first bit (msb) of spi instruction on the si pin. further, all data inputs and outputs are sy nchronized with sck. data transmission si/so spi data bus consists of two lines, si and so, for serial data communication. the si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to the slave through the si pin, while the slave responds through the so pin. multip le slave devices may share the si and so lines as described earlier. cy14x064pa has two separate pins for si and so, whi ch can be connected with the master as shown in figure 3 on page 7 . most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 64kbit serial nvsram requires a 2byte address for any read or write operation. however, since the address is only 13 bits, it implies that the first three bits which are fed in are ignored by the device. although these three bits ar e dont care, cypress recommends that these bits are treated as 0 s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the inte nded operation. cy14x064pa uses the standard opcodes for memory acc esses. in addition to the memory accesses, cy14x064pa prov ides additional opcodes for the nvsram specific function s: store, recall, autostore enable, and autostore disable. re fer to table 1 on page 9 for details on opcodes. invalid opcode if an invalid opcode is received, the opcode is ign ored and the device ignores any additional serial data on the si pin until the next falling edge of cs and the so pin remains tristated. status register cy14x064pa has an 8bit status register. the bits i n the status register are used to configure the spi bus. these b its are described in the table 3 on page 10 . [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 7 of 43 spi modes cy14x064pa device may be driven by a microcontrolle r with its spi peripheral running in either of these two modes : spi mode 0 (cpol=0, cpha=0) spi mode 3 (cpol=1, cpha=1) for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge aft er cs goes active. if the clock starts from a high state (in m ode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck. the two spi modes are shown in figure 4 and figure 5 . the status of clock when the bus master is in standby m ode and not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 cpol and cpha bits must be set in the spi controlle r for the either mode 0 or mode 3. cy14x064pa detects the spi mode from the status of sck pin when device is selected by bringing the cs pin low. if sck pin is low when the device is sele cted, spi mode 0 is assumed and if sck pin is high, cy14x 064pa works in spi mode 3. figure 3. system configuration using spi nvsram cy14x064pa cy14x064pa u c o n tro lle r s c k m o s i m is o s i s o o s i s k c s s c k c s h o l d h o l d c s c s 1 c s 2 h o l d 1 h o l d 2 figure 4. spi mode 0 lsb msb 7 6 5 4 3 2 1 0 cs scksi 0 1 2 3 4 5 6 7 figure 5. spi mode 3 cs scksi 7 6 5 4 3 2 1 0 lsb msb 0 1 2 3 4 5 6 7 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 8 of 43 spi operating features power-up powerup is defined as the condition when the power supply is turned on and v cc crosses v switch voltage. during this time, the cs must be enabled to follow the v cc voltage. therefore, cs must be connected to v cc through a suitable pullup resistor. as a built in safety feature, cs is both edge sensitive and level sensitive. after powerup, the device is not select ed until a falling edge is detected on cs . this ensures that cs must have been high before going low to start the first operation. as described earlier, nvsram performs a power up re call operation after powerup and, therefore, all memory accesses are disabled for t fa duration after powerup. the hsb pin can be probed to check the ready/busy status of nvsram aft er powerup. power-on reset a poweron reset (por) circuit is included to preve nt inadvertent writes. at powerup, the device does not respond to any instruction until the v cc reaches the por threshold voltage (v switch ). after v cc transitions the por threshold, the device is internally reset and performs a powerup recall operation. during power up recall all device accesses are inhi bited. the device is in the following state after por: deselected (after powerup, a falling edge is requi red on cs before any instructions are started). standby power mode not in the hold condition status register state: write enable (wen) bit is reset to 0. wpen, bp1, bp0 unchanged from previous store operation. the wpen, bp1, and bp0 bits of the status register are nonvolatile bits and remain unchanged from the prev ious store operation. prior to selecting and issuing instructions to the memory, a valid and stable v cc voltage must be applied. this voltage must remain valid until the end of the instruction trans mission. power down at powerdown (continuous decay of v cc ), when v cc drops from the normal operating voltage and below the v switch threshold voltage, the device stops responding to any instruc tion sent to it. if a write cycle is in progress and the last data b it d0 has been received when the power goes down, it is allowed t delay time to complete the write. after this, all memory accesses are inhibited and a conditional autostore operation is performed (autostore is not performed if no writes have happened since the last recall cycle). this feature prevents inadvertent writes to nvsram from happening during powerdown. however, to avoid the possibility of inadvertent writes during powerdown, ensure tha t the device is deselected and is in standby power mode and the cs follows the voltage applied on v cc . active power and standby power modes when cs is low, the device is selected and is in the activ e power mode. the device consumes i cc current, as specified in dc electrical characteristics on page 32 . when cs is high, the device is deselected and the device goes into the s tandby power mode after t sb time if a store or recall cycle is not in progress. if a store/recall cycle is in progress, t he device goes into the standby power mode after the store/re call cycle is completed. in the standby power mode the c urrent drawn by the device drops to i sb . [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 9 of 43 spi functional description the cy14x064pa uses an 8bit instruction register. instructions and their operation codes are listed i n table 3 . all instructions, addresses, and data are transferred with the msb fi rst and start with a high to low cs transition. there are, in all, 21 spi instructions that provide access to most of the functions in nvs ram. further, the wp , hold , and hsb pins provide additional functionality driven through hardware. the spi instructions in cy14x064pa are divided base d on their functionality in these types: status register control instructions: ? status register access: rdsr, fast_rdsr and wrsr instructions ? write protection and block protection: wren and wr di instructions along with wp pin and wen, bp0, and bp1 bits sram read/write instructions ? memory access: read, fast_read, and write instruc tions rtc read/write instructions ? rtc access: rdrtc, fast_rdrtc and wrtc instructions special nv instructions ? nvsram special instructions: store, recall, asenb, and asdisb special instructions: sleep, wrsn, rdsn, fast_rdsn, rdid, fast_rdid table 1. instruction set instruction category instruction name opcode operation status register control instructions status register access rdsr 0000 0101 read status register fast_rdsr 0000 1001 fast status register read spi c lock > 40 mhz wrsr 0000 0001 write status register write protection and block protection wren 0000 0110 set write enable latch wrdi 0000 0100 reset write enable latch sram read/write instructions memory access read 0000 0011 read data from memory array fast_read 0000 1011 fast read spi clock > 40 mhz write 0000 0010 write data to memory array rtc read/write instructions rtc access rdrtc 0001 0011 read rtc registers fast_rdrtc 0001 1101 fast rtc register read spi clo ck > 25 mhz wrtc 0001 0010 write rtc registers special nv instructions nvsram special functions store 0011 1100 software store recall 0110 0000 software recall asenb 0101 1001 autostore enable asdisb 0001 1001 autostore disable special instructions sleep sleep 1011 1001 sleep mode enable serial number wrsn 1100 0010 write serial number rdsn 1100 0011 read serial number fast_rdsn 1100 1001 fast serial number read spi clo ck > 40 mhz device id read rdid 1001 1111 read manufacturer jedec id and product id fast_rdid 1001 1001 fast manufacturer jedec id and pr oduct id read spi clock > 40 mhz reserved reserved 0001 1110 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 10 of 43 status register the status register bits are listed in table 2 . the status register consists of a ready bit (rdy ) and data protection bits bp1, bp0, wen, and wpen. the rdy bit can be polled to check the ready/busy status while a nvsram store or software recall cycle is in progress. the status register ca n be modified by wrsr instruction and read by rdsr or fast_rdsr instruction. however, only the wpen, bp1, and bp0 bits of the status register can be modified by using the wrsr instruction. the wrsr instruction has no effec t on wen and rdy bits. the default value shipped from the factory f or wen, bp0, bp1, bits 4 5, snl and wpen is 0. snl (bit 6) of the status register is used to lock the serial number written using the wrsn instruction. the seri al number can be written using the wrsn instruction multiple times while this bit is still '0'. when set to '1', this bit pr events any modification to the serial number. this bit is factory programme d to '0' and can only be written to once. after this bit is set to ' 1', it can never be cleared to '0'. read status register (rdsr) instruction the read status register instruction provides acces s to the status register at spi frequency up to 40 mhz. this instruction is used to probe the write enable status of the dev ice or the ready status of the device. rdy bit is set by the device to 1 whenever a store or software recall cycle is in pro gress. the block protection and wpen bits indicate the ext ent of protection employed. this instruction is issued after the falling edge o f cs using the opcode for rdsr. fast read status register (fast_rdsr) instruction the fast_rdsr instruction allows you to read the st atus register at spi frequency above 40 mhz and up to 10 4 mhz (max).this instruction is used to probe the write e nable status of the device or the ready status of the device. rd y bit is set by the device to 1 whenever a store or software reca ll cycle is in progress. the block protection and wpen bits indicate the extent of protection employed. this instruction is issued after the falling edge o f cs using the opcode for rdsr followed by a dummy byte. write status register (wrsr) instruction the wrsr instruction enables the user to write to t he status register. however, this instruction cannot be used to modify bit 0 (rdy ), bit 1 (wen) and bits 45 . the bp0 and bp1 bits can be used to select one of four levels of block protecti on. further, wpen bit must be set to 1 to enable the use of wr ite protect (wp ) pin. wrsr instruction is a write instruction and needs w rites to be enabled (wen bit set to 1) using the wren instruc tion before it is issued. the instruction is issued after the f alling edge of cs using the opcode for wrsr followed by eight bits of data to be stored in the status register. wrsr instruction can be used to modify only bits 2, 3, 6 and 7 of the status regist er. note in cy14x064pa, the values written to status registe r are saved to nonvolatile memory only after a store oper ation. if autostore is disabled, any modifications to the sta tus register must be secured by performing a software store oper ation. table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) snl (0) x (0) x (0) bp1 (0) bp0 (0) wen (0) rdy table 3. status register bit definition bit definition description bit 0 (rdy ) ready read only bit indicates the ready status of d evice to perform a memory access. this bit is set to 1 by the device while a store or software recall cycle is in progress. bit 1 (wen) write enable wen indicates if the device is write enabled. this bit defaults to 0 (disabled) on powerup. wen = '1' > write enabled wen = '0' > write disabled bit 2 (bp0) block protect bit 0 used for block prot ection. for details see table 4 on page 12 . bit 3 (bp1) block protect bit 1 used for block prot ection. for details see table 4 on page 12 . bit 45 dont care these bits are nonwritable and al ways return 0 upon read. bit 6 (snl) serial number lock set to '1' for locking serial number bit 7(wpen) write protect enable bit used for enablin g the function of write protect pin (wp ). for details see table 5 on page 12 . [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 11 of 43 write protection and block protection cy14x064pa provides features for both software and hardware write protection using wrdi instruction and wp . additionally, this device also provides block protection mechanism thr ough bp0 and bp1 pins of the status register. the write enable and disable status of the device i s indicated by wen bit of the status register. the write instructi ons (wrsr, write, wrtc and wrsn) and nvsram special instructio n (store, recall, asenb, asdisb) need the write to be enabled (wen bit = 1) before they can be issued. write enable (wren) instruction on powerup, the device is always in the write disa ble state. the following write, wrsr, wrtc, wrsn or nvsram special instruction must therefore be preceded by a write e nable instruction. if the device is not write enabled (we n = 0), it ignores the write instructions and returns to the s tandby state when cs is brought high. a new cs falling edge is required to reinitiate serial communication. the instruction i s issued following the falling edge of cs . when this instruction is used, the wen bit of status register is set to 1. wen b it defaults to 0 on powerup. note after completion of a write instruction (wrsr, write, wrtc or wrsn) or nvsram special instruction (store, recall, asenb, asdisb) instruction, wen bit is clea red to 0. this is done to provide protection from any inadver tent writes. therefore, wren instruction needs to be used before a new write instruction is issued. figure 6. read status register (rdsr) instruction timing figure 7. fast read status register (fast_rdsr) in struction timing figure 8. write status register (wrsr) instruction timing cssck so 0 1 2 3 4 5 6 7 si 0 0 0 0 0 1 0 0 1 hi-z 0 1 2 3 4 5 6 7 data lsb d0 d1 d2 d3 d4 d5 d6 msb d7 op-code cssck so 0 1 2 3 4 5 6 7 si 0 0 0 0 1 0 0 1 hi-z 8 9 10 11 12 13 14 15 0 data lsb d0 d1 d2 d3 d4 d5 d6 msb d7 x x x x x x x x dummy byte 0 1 2 3 4 5 6 7 op-code cs sck so 0 1 2 3 4 5 6 7 si 0 0 0 0 0 0 0 1 msb lsb d2 d3 d7 hi-z 0 1 2 3 4 5 6 7 opcode data in x x x x x [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 12 of 43 . write disable (wrdi) instruction write disable instruction disables the write by cle aring the wen bit to 0 to protect the device against inadverten t writes. this instruction is issued following the falling edge of cs followed by opcode for wrdi instruction. the wen bit is cleared on the rising edge of cs following a wrdi instruction. block protection block protection is provided using the bp0 and bp1 pins of the status register. these bits can be set using wrsr i nstruction and probed using the rdsr instruction. the nvsram i s divided into four array segments. onequarter, onehalf, or all of the memory segments can be protected. any data within t he protected segment is read only. table 4 shows the function of block protect bits. hardware write protection (wp pin) the write protect pin (wp ) is used to provide hardware write protection. wp pin enables all normal read and write operations when held high. when the wp pin is brought low and wpen bit is 1, all write operations to the status regi ster are inhibited. the hardware write protection function is blocked w hen the wpen bit is 0. this allows you to install the dev ice in a system with the wp pin tied to ground, and still write to the status register. wp pin can be used along with wpen and block protect bits (bp1 and bp0) of the status register to inhibit wri tes to memory. when wp pin is low and wpen is set to 1, any modificatio ns to status register are disabled. therefore, the mem ory is protected by setting the bp0 and bp1 bits and the w p pin inhibits any modification of the status register bits, provi ding hardware write protection. note wp going low when cs is still low has no effect on any of the ongoing write operations to the status register. table 5 summarizes all the protection features provided in the cy14x064pa. memory access all memory accesses are done using the read and wri te instructions. these instructions cannot be used whi le a store or recall cycle is in progress. a store cycle in pr ogress is indicated by the rdy bit of the status register and the hsb pin. read sequence (read) instruction the read operations on this device are performed by giving the instruction on the si pin and reading the output on so pin. the following sequence needs to be followed for a read operation: after the cs line is pulled low to select a device, the read opcode is transmitted through the si line followed by two bytes of address (a12a0). the most significant address b its (a15a13) are dont cares. after the last address b it is transmitted on the si pin, the data (d7d0) at the specific address is shifted out on the so line on the fallin g edge of sck starting with d7. any other data on si line after t he last address bit is ignored. cy14x064pa allows reads to be performed in bursts t hrough spi which can be used to read consecutive addresses without issuing a new read instruction. if only one byte is to be read, the cs line must be driven high after one byte of data co mes out. however, the read sequence may be continued by holding the cs line low and the address is automatically incremen ted and data continues to shift out on so pin. when the last data memory address (0x1fff) is reached, the address rol ls over to 0x0000 and the device continues to read. fast read sequence (fast_read) instruction the fast_read instruction allows you to read memory at spi frequency above 40 mhz and up to 104 mhz (max). the host system must first select the device by driving cs low, the fast_read instruction is then written to si, follow ed by 2 address byte (a12a0) and then a dummy byte. the mo st significant address bits (a15a13) are dont cares. from the subsequent falling edge of the sck, the da ta of the specific address is shifted out serially on the so line starting with msb. the first byte specified can be at any location. th e device figure 9. wren instruction figure 10. wrdi instruction table 4. block write protect bits level status register bits array addresses protected bp1 bp0 0 0 0 none 1 (1/4) 0 1 0x18000x1fff 2 (1/2) 1 0 0x10000x1fff 3 (all) 1 1 0x00000x1fff 0 0 0 0 0 1 1 0 cs scksi so hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 table 5. write protection operation wpen wp wen protected blocks unprotected blocks status register x x 0 protected protected protected 0 x 1 protected writable writable 1 low 1 protected writable protected 1 high 1 protected writable writable [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 13 of 43 automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single fast_read instruction. when the highest address in the memory array is reached, address cou nter rolls over to start address 0x0000 and thus allowing the read sequence to continue indefinitely. the fast_read in struction is terminated by driving cs high at any time during data output. note fast_read instruction operates up to maximum of 104 mhz spi frequency. write sequence (write) instruction the write operations on this device are performed t hrough the si pin. to perform a write operation, if the device is write disabled, then the device must first be write enabled through the wren instruction. when the writes are enabled (wen = 1 ), write instruction is issued after the falling edge of cs . a write instruction constitutes transmitting the write opco de on si line followed by two bytes of address (a12 a0) and the data (d7d0) which is to be written. the most significant addres s bits (a15 a13) are dont cares. cy14x064pa enables writes to be performed in bursts through spi which can be used to write consecutive addresse s without issuing a new write instruction. if only one byte i s to be written, the cs line must be driven high after the d0 (lsb of data ) is transmitted. however, if more bytes are to be writt en, cs line must be held low and address is incremented automat ically. the following bytes on the si line are treated as d ata bytes and written in the successive addresses. when the last data memory address (0x1fff) is reached, the address rolls over to 0x0000 and the device continues to write. the wen bit is r eset to 0 on completion of a write sequence. note when a burst write reaches a protected block addre ss, it continues the address increment into the protected space but does not write any data to the protected memory. if the address roll over takes the burst write to unprotected spac e, it resumes writes. the same operation is true if a burst write is initiated within a write protected block. figure 11. read instruction timing figure 12. burst mode read instruction timing ~ ~ cssck so 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 0 1 2 3 4 5 6 7 msb lsb data si ~ ~ op-code 0 0 0 0 0 0 1 x x x a12 a11 a9 1 a10 a8 a3 a1 a2 a0 13-bit address msb lsb d0 d1 d2 d3 d4 d5 d6 d7 hi-z cssck so lsb si op-code 13-bit address msb lsb ~ ~ ~ ~ ~ ~ 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ~ ~ 0 7 0 0 0 0 0 0 1 1 x x x a12 a11 a10 a9 a8 a3 a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7 data byte 1 data byte n msb lsb msb d0 d1 d2 d3 d4 d5 d6 d7 d0 d7 hi-z [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 14 of 43 figure 13. fast read instruction timing figure 14. write instruction timing figure 15. burst mode write instruction timing ~ ~ cssck so 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 23 data si ~ ~ op-code 0 0 0 0 1 0 1 x x a12 a11 a9 1 a10 a8 a3 a1 a2 a0 13-bit address b s l b s m msb lsb d0 d1 d2 d3 d4 d5 d6 d7 0 1 2 3 4 5 6 7 x x x x x x x x dummy byte hi-z x ~ ~ cssck so 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 0 1 2 3 4 5 6 7 msb lsb data d0 d1 d2 d3 d4 d5 d6 d7 si ~ ~ op-code 0 0 0 0 0 0 1 x x x a11 a9 0 a10 a8 a3 a1 a2 a0 13-bit address msb lsb hi-z a12 ~ ~ cssck so msb lsb si op-code 13-bit address msb lsb ~ ~ ~ ~ 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ~ ~ 0 7 0 0 0 0 0 0 1 0 x x x a12 a11 a10 a9 a8 a3 a2 a1 a0 hi-z data byte 1 data byte n d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d7 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 15 of 43 rtc access cy14x064pa uses 16 registers for rtc. these registe rs can be read out or written to by accessing all 16 register s in burst mode or accessing each register, one at a time. the rdrt c, fast_rdrtc, and wrtc instructions are used to acces s the rtc. all the rtc registers can be read in burst mode by issuing the rdrtc and fast_rdrtc instruction and reading all 16 bytes without bringing the cs pin high. the r bit must be set while reading the rtc timekeeping registers to ensure tha t transitional values of time are not read. writes to the rtc register are performed using the wrtc instruction. writing rtc timekeeping registers and control registers, except for the flags register needs the w bit of the flags register to be set to 1. the internal count ers are updated with the new date and time setting when the w bit is cleared to 0. all the rtc registers can also be written in b urst mode using the wrtc instruction. read rtc (rdrtc) instruction read rtc (rdrtc) instruction allows you to read the contents of rtc registers at spi frequency upto 25 mhz. read ing the rtc registers through the so pin requires the follo wing sequence: after the cs line is pulled low to select a device, the rdrtc opcode is transmitted through the si line fol lowed by eight address bits for selecting the register. any data on the si line after the address bits is ignored. the data (d 7d0) at the specified address is then shifted out onto the so l ine. rdrtc also allows burst mode read operation. when reading multiple bytes from rtc registers, the address rolls over to 0x00 after the last rtc register address (0x0f) is reached. the r bit in rtc flags register must be set to 1 before reading rtc time keeping registers to avoid reading transit ional data. modifying the rtc flag registers requires a write r tc cycle. the r bit must be cleared to '0' after completion of th e read operation. the easiest way to read rtc registers is to perform rdrtc in burst mode. the read may start from the first rtc r egister (0x00) and the cs must be held low to allow the data from all 16 rtc registers to be transmitted through the so pin. note rdrtc instruction operates at a maximum clock frequency of 25 mhz. the opcode cycles, address cyc les and data out cycles need to run at 25 mhz for the instr uction to work properly. fast read sequence (fast_rdrtc) instruction the fast_rdrtc instruction allows you to read memor y at a spi frequency above 25 mhz and up to 104 mhz (max). the host system must first select the device by driving cs low, the fast_read instruction is then written to si, follow ed by 8 bit address and a dummy byte. from the subsequent falling edge of the sck, the da ta of the specific address is shifted out serially on the so line starting with msb. the first byte specified can be at any locatio n. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single fast_rdrtc instruction. when the highest address (0x0f) in the memory array is reached, the address counter rolls over to start address 0x00 and thus a llowing the read sequence to continue indefinitely. the fast_rd rtc instruction is terminated by driving cs high at any time during data output. note fast_read instruction operates up to max of 104 mh z spi frequency. figure 16. read rtc (rdrtc) instruction timing cssck so 0 1 2 3 4 5 6 7 0 3 2 1 4 5 6 7 0 1 2 3 4 5 6 7 msb lsb data si op-code 0 0 0 1 0 0 1 0 0 0 0 1 a3 a1 a2 a0 msb lsb d0 d1 d2 d3 d4 d5 d6 d7 hi-z [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 16 of 43 figure 17. fast rtc read (fast_rdrtc) instruction timing write rtc (wrtc) instruction write rtc (wrtc) instruction allows you to modify t he contents of rtc registers. the wrtc instruction req uires the wen bit to be set to '1' before it can be issued. i f wen bit is '0', a wren instruction needs to be issued before using wrtc. writing rtc registers requires the following sequen ce: after the cs line is pulled low to select a device, wrtc opcode is transmitted through the si line followed by eight a ddress bits identifying the register which is to be written to and one or more bytes of data. wrtc allows burst mode write operati on. when writing more than one registers in burst mode, the address rolls over to 0x00 after the last rtc address (0x0f) is r eached. note that writing to rtc timekeeping and control re gisters require the w bit to be set to '1'. the values in t hese rtc registers take effect only after the w bit is cle ared to '0'. write enable bit (wen) is automatically cleared to 0 af ter completion of the wrtc instruction. cssck so 0 1 2 3 4 5 6 7 0 3 2 1 4 5 6 7 8 9 10 11 12 13 14 15 si op-code 0 0 0 1 1 1 0 0 0 0 0 1 a3 a1 a2 a0 msb lsb msb lsb data d0 d1 d2 d3 d4 d5 d6 d7 x x x x x x x x 16 17 18 19 20 21 22 23 dummy byte hi-z figure 18. write rtc (wrtc) instruction timing cssck so 0 1 2 3 4 5 6 7 0 3 2 1 4 5 6 7 0 1 2 3 4 5 6 7 si op-code 0 0 0 1 0 0 1 0 0 0 0 0 a3 a1 a2 a0 4-bit address msb lsb msb lsb data hi-z d0 d1 d2 d3 d4 d5 d6 d7 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 17 of 43 nvsram special instructions cy14x064pa provides four special instructions that allow access to the nvsram specific functions: store, rec all, asdisb, and asenb. table 6 lists these instructions. software store (store) instruction when a store instruction is executed, cy14x064pa pe rforms a software store operation. the store operation is performed regardless of whether or not a write has taken place since the last store or recall operation. to issue this instruction, the device must be write enabled (wen bit = 1).the instruction is performed by transmit ting the store opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the store instruction. software recall (recall) instruction when a recall instruction is executed, cy14x064pa performs a software recall operation. to issue this instruction, the device must be write enabled (wen = 1). the instruction is performed by transmitting the re call opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the recall instruction. . autostore enable (asenb) instruction the autostore enable instruction enables the autost ore on cy14x064pa. this setting is not nonvolatile and nee ds to be followed by a store sequence if this is desired to survive the power cycle. to issue this instruction, the device must be write enabled (wen = 1). the instruction is performed by transmittin g the asenb opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the asenb instruction. autostore disable (asdisb) instruction autostore is enabled by default in cy14x064pa. the autostore disable instruction disables the autostore on cy14x 064pa. this setting is not nonvolatile and needs to be fol lowed by a store sequence if this is desired to survive the po wer cycle. to issue this instruction, the device must be write enabled (wen = 1). the instruction is performed by transmittin g the asdisb opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the asdisb instruction. . special instructions sleep instruction sleep instruction puts the nvsram in sleep mode. wh en the sleep instruction is issued and cs is brought high, the nvsram performs a store operation to secure the dat a to nonvolatile memory and then enters into sleep mode. the device starts consuming i zz current after t sleep time from the instance when sleep instruction is registered. the device is not accessible for normal operations after sleep instru ction is issued. once in sleep mode, the sck and si pins are ignored and so will be hiz but device continues to monitor the cs pin. table 6. nvsram special instructions function name opcode operation store 0011 1100 software store recall 0110 0000 software recall asenb 0101 1001 autostore enable asdisb 0001 1001 autostore disable figure 19. software store operation figure 20. software recall operation 0 0 1 1 1 1 0 0 cs scksi so hi-z 0 1 2 3 4 5 6 7 0 1 1 0 0 0 0 0 cssck si 0 1 2 3 4 5 6 7 so hi-z figure 21. autostore enable operation figure 22. autostore disable operation 0 1 0 1 1 0 0 1 cs scksi so hi-z 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 cs scksi so hi-z 0 1 2 3 4 5 6 7 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 18 of 43 to wake the nvsram from the sleep mode, the device must be selected by toggling the cs pin from high to low . the device wakes up and is accessible for normal operations af ter t wake duration after a falling edge of cs pin is detected. note whenever nvsram enters into sleep mode, it initiat es nonvolatile store cycle which results in an enduran ce cycle per sleep command execution. a store cycle starts only if a write to the sram has been performed since the last store or recall cycle. serial number the serial number is an 8byte programmable memory space provided to you to uniquely identify this device. i t typically consists of a two byte customer id, followed by fiv e bytes of unique serial number and one byte of crc check. how ever, nvsram does not calculate the crc and it is up to t he system designer to utilize the eight byte memory space in whatever manner desired. the default value for eight byte lo cations are set to 0x00. wrsn (serial number write) instruction the serial number can be written using the wrsn ins truction. to write serial number the write must be enabled using the wren instruction. the wrsn instruction can be used in bu rst mode to write all the 8 bytes of serial number. the serial number is locked using the snl bit of th e status register. once this bit is set to '1', no modificat ion to the serial number is possible. after the snl bit is set to '1' , using the wrsn instruction has no effect on the serial number. a store operation (autostore or software store) is required to store the serial number in nonvolatile memory. i f autostore is disabled, you must perform a software store operati on to secure and lock the serial number. if snl bit is se t to 1 and is not stored (autostore disabled), the snl bit and se rial number defaults to 0 at the next power cycle. if snl bit is set to 1 and is stored, the snl bit can never be cleared to 0. this instruction requires the wen bit to be set before it can be exe cuted. the wen bit is reset to '0' after completion of this in struction. figure 23. sleep mode entry 1 0 1 1 1 0 0 1 cs scksi so hi-z 0 1 2 3 4 5 6 7 t sleep figure 24. wrsn instruction ~ ~ cssck so 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 56 57 58 59 60 61 62 63 lsb d0 d1 d2 d3 d4 d5 d6 d7 si op-code 1 1 0 0 0 0 1 0 8-byte serial number msb hi-z d7 d6 d5 d4 d3 d2 d1 d0 ~ ~ byte - 8 byte - 1 [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 19 of 43 rdsn (serial number read) instruction the serial number is read using rdsn instruction at spi frequency upto 40 mhz. a serial number read ma y be performed in burst mode to read all the eight bytes at once. after the last byte of serial number is read, the device doe s not loop back. rdsn instruction can be issued by shifting the opcode for rdsn in t hrough the si pin of nvsram after cs goes low. this is followed by nvsram shifting out the eight bytes of serial number throu gh the so pin. fast_rdsn (fast serial number read) instruction the fast_rdsn instruction is used to read serial nu mber at spi frequency above 40 mhz and up to 104 mh z (max). a serial number read may be performed in burst mode to read all the eight bytes at once. after the last byte of serial number is read, the device does not loop back. fast_rdsn instruction can be issued by shifting the opcode for fast_rdsn in through th e si pin of nvsram followed by dummy byte after cs goes low. this is followed by nvsram shifting out the eight bytes of serial number through the so pin. figure 25. rdsn instruction cssck so 0 1 2 3 4 5 6 7 si op-code 1 1 0 0 0 0 1 1 ~ ~ lsb d0 d1 d2 d3 d4 d5 d6 d7 8-byte serial number msb d7 d6 d5 d4 d3 d2 d1 d0 byte - 8 byte - 1 0 7 6 5 4 3 2 1 56 57 58 59 60 61 62 63 ~ ~ hi-z figure 26. fast_rdsn instruction cssck so 0 1 2 3 4 5 6 7 si op-code 1 1 0 0 1 0 0 1 ~ ~ lsb d0 d1 d2 d3 d4 d5 d6 d7 8-byte serial number msb d7 d6 d5 d4 d3 d2 d1 d0 byte - 8 byte - 1 0 7 6 5 4 3 2 1 56 57 58 59 60 61 62 63 ~ ~ x x x x x x x x dummy byte 8 9 10 11 12 13 14 15 hi-z [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 20 of 43 device id device id is a 4byte read only code identifying a type of product uniquely. this includes the product family code, configuration, and density of the product. the device id is divided into four parts as shown i n table 9 : 1. manufacturer id (11 bits) this is the jedec assigned manufacturer id for cypr ess. jedec assigns the manufacturer id in different bank s. the first three bits of the manufacturer id represent the ban k in which id is assigned. the next eight bits represent the manu facturer id. cypresss manufacturer id is 0x34 in bank 0. theref ore the manufacturer id for all cypress nvsram products is: cypress id 000_0011_0100 2. product id (14 bits) the product id for device is shown in the table 9 . 3. density id (4 bits) the 4 bit density id is used as shown in table 9 for indicating the 64 kb density of the product. 4. die rev (3 bits) this is used to represent any major change in the d esign of the product. the initial setting of this is always 0x0. rdid (device id read) instruction this instruction is used to read the jedec assigned manufacturer id and product id of the device at spi frequency upto 40 mhz. this instruction can be used to identif y a device on the bus. rdid instruction can be issued by shifting the opcode for rdid in through the si pin of nvsram after cs goes low. this is followed by nvsram shifting out the four by tes of device id through the so pin. table 7. device id bits #of bits 31 - 21 (11 bits) 20 - 7 (14 bits) 6 - 3 (4 bits) 2 - 0 (3 bits) device manufacturer id product id density id die rev cy14c064pa 00000110100 00001110000001 0001 000 cy14b064pa 00000110100 00001110010001 0001 000 cy14e064pa 00000110100 00001110100001 0001 000 figure 27. rdid instruction 1 0 0 1 1 1 1 1 cs scksi so hi-z 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 msb 4-byte device id d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 lsb d0 d1 d2 d3 d4 d5 d6 d7 byte - 4 byte - 3 byte - 2 byte - 1 op-code [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 21 of 43 fast_rdid (fast device id read) instruction the fast_rdid instruction allows you to read the je dec assigned manufacturer id and product id at spi frequency above 40 mhz and up to 104 mhz (max). fast_rdid instruction can be issued by shifting the opcode for fast_rdid in through the si pin of nvsram followed by dummy byte after cs goes low. this is followed by nvsram shifting out the four bytes of device id through the so pin. hold pin operation the hold pin is used to pause the serial communication. whe n the device is selected and a serial sequence is und erway, hold is used to pause the serial communication with the master device without resetting the ongoing serial sequence. to p ause, the hold pin must be brought low when the sck pin is low. t o resume serial communication, the hold pin must be brought high when the sck pin is low (sck may toggle during hold ). while the device serial communication is paused, in puts to the si pin are ignored and the so pin is in the highim pedance state. this pin can be used by the master with the cs pin to pause the serial communication by bringing the pin hold low and deselecting an spi slave to establish communication with another slave device, without the serial communicat ion being reset. the communication may be resumed at a later point by selecting the device and setting the hold pin high. figure 28. fast_rdid instruction 1 0 0 1 1 0 0 1 cs scksi so hi-z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 msb 4-byte device id d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 lsb d0 d1 d2 d3 d4 d5 d6 d7 byte - 4 byte - 3 byte - 2 byte - 1 x x x x x x x x dummy byte 24 25 26 27 28 29 30 31 op-code figure 29. hold operation ~ ~ ~ ~ cs sckhold so [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 22 of 43 real time clock operation nvtime operation the cy14x064pa offers internal registers that conta in clock, alarm, watchdog, interrupt, and control functions. the rtc registers occupy a separate address space from nvsr am and are accessible through rdrtc and wrtc instructions on register addresses 0x00 to 0x0f. internal double bu ffering of the clock and the timer information registers prevents accessing transitional internal clock data during a read or w rite operation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in onesecond increments. the time can be set to any c alendar time and the clock automatically keeps track of day s of the week and month, leap years, and century transitions. the re are eight registers dedicated to the clock functions, which a re used to set time with a write cycle and to read time during a r ead cycle. these registers contain the time of day in bcd form at. bits defined as 0 are currently not used and are reser ved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. the user must stop internal updates to the cy14x064pa time keeping reg isters before reading clock data, to prevent reading of da ta in transition. stopping the register updates does not affect clock accuracy. the updating process is stopped by writing a 1 to the read bit r (in the flags register at 0x00), and does not r estart until a 0 is written to the read bit. the rtc registers are r ead while the internal clock continues to run. after a 0 is wri tten to the read bit (r), all rtc registers are simultaneously updated within 20 ms. setting the clock setting the write bit w (in the flags register at 0x00) to a 1 stops updates to the time keeping registers and enables t he time to be set. the correct day, date, and time is then writte n into the registers and must be in 24hour bcd format. the ti me written is referred to as the base time. this value is st ored in nonvolatile registers and used in the calculation o f the current time. resetting the write bit to 0 transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. if the time written to the timekeeping registers is not in the correct bcd format, each invalid nibble of the rtc register s continue counting to 0xf before rolling over to 0x0 after wh ich rtc resumes normal operation. note after w bit is set to 0, values written into th e timekeeping, alarm, calibration, and interrupt registers are tra nsferred to the rtc time keeping counters in t rtcp time. these counter values must be saved to nonvolatile memory either by initi ating a software/hardware store or autostore operation. whi le working in autostore disabled mode, perform a store operation after t rtcp time while writing into the rtc registers for the modifications to be correctly recorded. backup power the rtc in the cy14x064pa is intended for permanent ly powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chos en for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, whic h maximizes the backup time available from the backup source. regar dless of the clock operation with the primary source removed, th e data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during backup operation, the cy14x064pa consumes a 0.35 a (typ) at room temperature. the user must choose cap acitor or battery values according to the application. backup time values based on maximum current specifi cations are shown in table 8 . nominal backup times are approximately two times longer. using a capacitor has the obvious advantage of rech arging the backup source each time the system is powered up. i f a battery is used, a 3v lithium is recommended and the cy14x 064pa sources current only from the battery when the prim ary power is removed. however, the battery is not recharged at a ny time by the cy14x064pa. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. stopping and starting the oscillator the oscen bit in the calibration register at 0x08 c ontrols the enable and disable of the oscillator. this bit is n onvolatile and is shipped to customers in the enabled (set to 0) state. to preserve the battery life when the system is in sto rage, oscen must be set to 1. this turns off the oscillator c ircuit, extending the battery life. if the oscen bit goes from disabl ed to enabled, it takes approximately one second (two seconds maxi mum) for the oscillator to start. while system power is off, if the voltage on the ba ckup supply (v rtccap or v rtcbat ) falls below their respective minimum level, the oscillator may fail.the cy14x064pa has the abil ity to detect oscillator failure when system power is restored. t his is recorded in the oscillator fail flag (oscf) of the flags reg ister at the address 0x00. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for enabled status. if the oscen bit is enabled and the oscillator is not acti ve within the first 5 ms, the oscf bit is set to 1. the system must check for this condition and then write 0 to clear the flag . note that in addition to setting the oscf flag bit, the time reg isters are reset to the base time (see setting the clock on page 22 ), which is the value last written to the timekeeping registers . the control or calibration registers and the oscen bit are not affected by the oscillator failed condition. table 8. rtc backup time capacitor value backup time (cy14b064pa) 0.1f 60 hours 0.47f 12 days 1.0f 25 days [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 23 of 43 the value of oscf must be reset to 0 when the tim e registers are written for the first time. this initializes th e state of this bit which may have become set when the system was first powered on. to reset oscf, set the write bit w (in the flags register at 0x00) to a 1 to enable writes to the flags register. wr ite a 0 to the oscf bit and then reset the write bit to 0 to dis able writes. calibrating the clock the rtc is driven by a quartz controlled crystal wi th a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystals availa ble in market typically have an error of + 20 ppm to + 35 ppm. however, cy14x064pa employs a calibration circuit that impro ves the accuracy to +1/C2 ppm at 25 c. this implies an error of +2.5 seconds to 5 seconds per month. the calibration circuit adds or subtracts counts from t he oscillator divider circuit to achieve this accuracy. the numbe r of pulses that are suppressed (subtracted, negative calibration) o r split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0 x08. the calibration bits occupy the five lower order bits i n the calibration register. these bits are set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where a 1 indicates positive calibration and a 0 indicates negative c alibration. adding counts speeds the clock up and subtracting c ounts slows the clock down. if a binary 1 is loaded into the register, it corresponds to an adjustment of 4.068 or C2.034 ppm offset in oscillator error, depending on the sign. calibration occurs within a 64minute cycle. the fi rst 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary 1 is loaded into the register, only the first two minute s of the 64minute cycle are modified. if a binary 6 is load ed, the first 12 are affected, and so on. therefore, each calibratio n step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.06 8 or C2.034 ppm of adjustment per calibration step in the calibrati on register. to determine the required calibration, the cal bit in the flags register (0x00) must be set to 1. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviat ion measured from the 512 hz indicates the degree and d irection of the required correction. for example, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value o f C10 (001010b) must be loaded into the calibration regis ter to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the write bit w (in the flags register at 0x00) to 1 to enable writes to the flags register . write a value to cal, and then reset the write bit to 0 to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the registers 0x015) with the corresponding time of day and date values. when a m atch occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie ) bit is set. there are four alarm match fields: date, hours, min utes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match l ogic. setting the match bit to 0 indicates that the corresponding f ield is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as freque ntly as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is d isabled. selecting all match bits (all 0s) causes an exact t ime and date match. there are two ways to detect an alarm event: by rea ding the af flag or monitoring the int pin. the af flag in the flags register at 0x00 indicates that a date or time match has occurr ed. the af bit is set to 1 when a match occurs. reading the flags register clears the alarm flag bit (and all others). a hardw are interrupt pin may also be used to detect an alarm event. to set, clear or enable an alarm, set the w bit ( in the flags register 0x00) to 1 to enable writes to alarm r egisters. after writing the alarm value, clear the w bit back to 0 for the changes to take effect. note cy14x064pa requires the alarm match bit for seconds (0x02 d7) to be set to 0 for proper operation o f alarm flag and interrupt. watchdog timer the watchdog timer is a free running down counter t hat uses the 32 hz clock (31.25 ms) derived from the crystal osc illator. the oscillator must be running for the watchdog to func tion. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a fre e running counter. on powerup, the watchdog time out value i n register 0x07 is loaded into the counter load register. coun ting begins on powerup and restarts from the loadable value any t ime the watchdog strobe (wds) bit is set to 1. the counte r is compared to the terminal value of 0. if the counter reache s this value, it causes an internal flag and an optional interrupt o utput. you can prevent the time out interrupt by setting wds bit t o 1 prior to the counter reaching 0. this causes the counter to re load with the watchdog time out value and to be restarted. as lon g as the user sets the wds bit prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watc hdog write bit to 0. when the wdw is 0, new writes to the watc hdog time out value bits d5d0 are enabled to modify the time out value. when wdw is 1, writes to bits d5d0 are ignored. the w dw function enables you to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 30 on page 24 . note that setting the watchdog time out value to 0 disables the watchdog function. the output of the watchdog timer is the flag bit wd f that is set if the watchdog is allowed to time out. if the watchdo g interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared wh en user reads the flag registers. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 24 of 43 . programmable square wave generator the square wave generator block uses the crystal ou tput to generate a desired frequency on the int pin of the device. the output frequency can be programmed to be one of the se: 1. 1hz 2. 512 hz 3. 4096 hz 4. 32768 hz the square wave output is not generated while the d evice is running on backup power. power monitor the cy14x064pa provides a power management scheme w ith power fail interrupt capability. it also controls t he internal switch to backup power for the clock and protects the memo ry from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to v switch threshold. as described in the section autostore operation on page 4 , when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvo latile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and wri te operations to nvsram are inhibited and the rtc func tions are not available to the user. the rtc clock continues to operate in the background. the updated rtc time keeping regist ers are available to the user after v cc is restored to the device (see autostore or powerup recall on page 37 ). backup power monitor the cy14x064pa provides a backup power monitoring s ystem which detects the backup power (either battery or c apacitor backup) failure. the backup power fail flag (bpf) i s issued on the next powerup in case of backup power failure. the bpf flag is set in the event of backup voltage falling lower than v bakfail . the backup power is monitored even while the rtc is running in backup mode. low voltage detected during backup mode is flagged through the bpf flag. bpf can hold the data only until a defined low level of the backup voltage (v dr ). interrupts the cy14x064pa has a flags register, interrupt regi ster, and interrupt logic that can signal interrupt to the mi crocontroller. there are three potential sources for interrupt: wa tchdog timer, power monitor, and alarm timer. each of these can b e individually enabled to drive the int pin by appropriate setting in the interrupt register (0x06). in addition, each has an associate d flag bit in the flags register (0x00) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raise d by one of the three sources and the respective interrupt enable b it in interrupts register is enabled (set to 1). after an interrup t source is active, two programmable bits, h/l and p/l, determine the b ehavior of the output pin driver on int pin. these two bits ar e located in the interrupt register and can be used to drive level o r pulse mode output from the int pin. in pulse mode, the pulse w idth is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags register is rea d by the user. this mode is used as an interrupt to a host microcontrol ler. the control bits are summarized in the section interrupt register . interrupts are only generated while working on norm al power and are not triggered when system is running in backup power mode. note cy14x064pa generates valid interrupts only after t he powerup recall sequence is completed. all events o n int pin must be ignored for t fa duration after powerup. interrupt register watchdog interrupt enable (wie) : when set to 1, the watchdog timer drives the int pin and an internal f lag when a watchdog time out occurs. when wie is set to 0, t he watchdog timer only affects the wdf flag in flags register. alarm interrupt enable (aie): when set to 1, the alarm match drives the int pin and an internal flag. when aie i s set to 0, the alarm match only affects the af flag in flags regis ter. power fail interrupt enable (pfe): when set to 1, the power fail monitor drives the pin and an internal flag. w hen pfe is set to 0, the power fail monitor only affects the pf flag in flags register. square wave enable (sqwe): when set to 1, a square wave of programmable frequency is generated on the int p in. the frequency is decided by the sq1 and sq0 bits of the interrupts register. this bit is nonvolatile and survives powe r cycle. the sqwe bit over rides all other interrupts. however, cal bit will take precedence over the square wave generator. thi s bit defaults to 0 from factory. figure 30. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32.768 khz [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 25 of 43 high/low (h/l): when set to a 1, the int pin is active high and the driver mode is push pull. the int pin drive s high only when v cc is greater than v switch . when set to a 0, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to vcc by a 10 k resistor while u sing the interrupt in active low mode. pulse/level (p/l): when set to a 1 and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/ l is set to a 0, the int pin is driven high or low (determined by h/l) until the flags register is read. sq1 and sq0 . these bits are used together to fix the frequency of square wave on int pin output when sqwe bit is s et to 1 . these bits are nonvolatile and survive power cycle. the output frequency is decided as per the following table. when an enabled interrupt source activates the int pin, an external host reads the flag registers to determine the cause. remember that all flag are cleared when the registe r is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive stat e. if the pin is programmed for pulse mode, then reading the flag al so clears the flag and the pin. the pulse does not complete i ts specified duration if the flags register is read. if the int pin is used as a host reset, the flags register is not read during a reset. this summary table shows the state of the int pin. flags register the flags register has three flag bits: wdf, af, an d pf, which can be used to generate an interrupt. these flag ar e set by the watchdog timeout, alarm match, or power fail monito r respectively. the processor can either poll this register or enab le interrupts to be informed when a flag is set. these flags are automatically reset after the register is read. the flags register is automatically loaded with the value 0x00 on poweru p (except for the oscf bit. see stopping and starting the oscillator on page 22 ). table 9. sqw output selection sq1 sq0 frequency comment 0 0 1 hz 1 hz signal 0 1 512 hz useful for calibration 1 0 4096 hz 4 khz clock output 1 1 32768 hz oscillator output frequency table 10. state of the int pin cal sqwe wie/aie/ pfe int pin output 1 x x 512 hz 0 1 x square wave output 0 0 1 alarm 0 0 0 hiz [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 26 of 43 figure 31. rtc recommended component configuration figure 32. interrupt block diagram recommended values y1 = 32.768 khz (12.5 pf) c 1 = 12 pf c 2 = 69 pf x out x in y1 c2 c1 note: the recommended values for c1 and c2 include board trace capacitance. wdf watchdog timer flag wie watchdog interrupt pf power fail flag pfe power fail enable af alarm fag aie alarm interrupt enable p/l pulse level h/l high/low enable pin driver wie wdf watchdog timer pfe pf aie af clock alarm p/l h/l v cc v ss int sqwe cal mux 512 hz clock square wave priority encoder wie/pie/ aie hi-z control sel line power monitor sqwe square wave enable [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 27 of 43 table 11. rtc register map [2, 3] register bcd format data function/range d7 d6 d5 d4 d3 d2 d1 d0 0x0f 10s years years years: 00C99 0x0e 0 0 0 10s months months months: 01C12 0x0d 0 0 10s day of month day of month day of month: 01C 31 0x0c 0 0 0 0 0 day of week day of week: 01C07 0x0b 0 0 10s hours hours hours: 00C23 0x0a 0 10s minutes minutes minutes: 00C59 0x09 0 10s seconds seconds seconds: 00C59 0x08 oscen (0) 0 cal sign (0) calibration (00000) calibration values [4] 0x07 wds (0) wdw (0) wdt (000000) watchdog [4] 0x06 wie (0) aie (0) pfe (0) sqwe (0) h/l (1) p/l (0) sq1 (0) sq0 (0) interrupts [4] 0x05 m (1) 0 10s alarm date alarm day alarm, day of mont h: 01C31 0x04 m (1) 0 10s alarm hours alarm hours alarm, hours: 0 0C23 0x03 m (1) 10s alarm minutes alarm minutes alarm, minut es: 00C59 0x02 m (1) 10s alarm seconds alarm seconds alarm, secon ds: 00C59 0x01 10s centuries centuries centuries: 00C99 0x00 wdf af pf oscf [5] bpf [5] cal (0) w (0) r (0) flags [4] notes 2. ( ) designates values shipped from the factory. 3. the unused bits of rtc registers are reserved for future use and should be set to 0. 4. this is a binary value, not a bcd value. 5. when user resets oscf and bpf flag bits, the flag s register will be updated after t rtcp time. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 28 of 43 table 12. register map detail register description 0x0f time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lowe r nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nib ble operates from 0 to 9. the range for the registe r is 0C99. 0x0e time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble (four bits) contains the lower digit and operates f rom 0 to 9; upper nibble (one bit) contains the upper digit and opera tes from 0 to 1. the range for the register is 1C12 . 0x0d time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble (four bits) contains the lower digit a nd operates from 0 to 9; upper nibble (two bits) contains the 10s digi t and operates from 0 to 3. the range for the regis ter is 1C31. leap years are automatically adjusted for. 0x0c time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that cor relates to day of the week. day of the week is a ri ng counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, because the day i s not integrated with the date. 0x0b time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble (four bits) contains the lower digit a nd operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the r egister is 0C23. 0x0a time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (fo ur bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digi t and operates from 0 to 5. the range for the regis ter is 0C59. 0x09 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (fo ur bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and op erates from 0 to 5. the range for the register is 0 C59. 0x08 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the oscill ator is stopped. when set to 0, the oscillator ru ns. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the timebase. calibration these five bits control the calibration of the clock. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 29 of 43 0x07 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit t o 0 has no effect. the bit is cleared automatically after the watchdog tim er is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 d isables any write to the watchdog timeout value (d5 Cd0). this enables the user to set the watchdog strobe bit without dis turbing the timeout value. setting this bit to 0 allows bits d5Cd0 to be written to the watchdog register when the next w rite cycle is complete. this function is explained in more detail in watchdog timer on page 23 . wdt watchdog timeout selection. the watchdog timer i nterval is selected by the 6bit value in this regi ster. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was set to 0 on a previous cycle. 0x06 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe sqwe h/l p/l sq1 sq0 wie watchdog interrupt enable. when set to 1 and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to 1, the ala rm match drives the int pin and the af flag. when s et to 0, the alarm match only affects the af flag. pfe power fail enable. when set to 1, the alarm ma tch drives the int pin and the pf flag. when set to 0, the power fail monitor affects only the pf flag. sqwe square wave enable. when set to 1, a square w ave is driven on the int pin with frequency program med using sq1 and sq0 bits. the square wave output takes preceden ce over interrupt logic. if the sqwe bit is set to 1. when an enabled interrupt source becomes active, only the c orresponding flag is raised and the int pin continu es to drive the square wave. h/l high/low. when set to 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to 1, the int pin is dri ven active (determined by h/l) by an interrupt sour ce for approximately 200 ms. when set to 0, the int pin is driven to a n active level (as set by h/l) until the flags register is read. sq1, sq0 sq1, sq0. these bits are used to decide the frequency of the square wave on the int pin output when sqwe bit is set to 1. the following is the frequency output f or each combination of (sq1, sq0): (0, 0) 1 hz (0, 1) 512 hz (1, 0) 4096 hz (1, 1) 32768 hz 0x05 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date val ue. m match. when this bit is set to 0, the date value is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. 0x04 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to 0, the hours valu e is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the hours value. table 12. register map detail (continued) register description [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 30 of 43 0x03 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value. m match. when this bit is set to 0, the minutes va lue is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minutes value. 0x02 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or deselect the seconds value. m match. when this bit is set to 0, the seconds va lue is used in the alarm match. setting this bit to 1 causes the match circuit to ignore the seconds value. 0x01 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibble c ontains the lower digit and operates from 0 to 9; u pper nibble contains the upper digit and operates from 0 to 9. the range for the register is 099 centuries. 0x00 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf bpf cal w r wdf watchdog timer flag. this read only bit is set t o 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags re gister is read or on powerup af alarm flag. this read only bit is set to 1 when the time and date match the values stored in the a larm registers with the match bits = 0. it is cleared when the flags register is read or on powerup. pf power fail flag. this read only bit is set to 1 when power falls below the power fail threshold v switch . it is cleared when the flags register is read. oscf oscillator fail flag. set to 1 on powerup if the oscillator is enabled and not running in the f irst 5 ms of operation. this indicates that rtc backup power failed and clock va lue is no longer valid. this bit survives power cyc le and is never cleared internally by the chip. the user must check for this condition and write '0' to clear this fla g. when user resets oscf flag bit, the bit will be updated after t rtcp time. bpf backup power fail flag. set to 1 on powerup i f the backup power (battery or capacitor) failed. t he backup power fail condition is determined by the voltage falling belo w their respective minimum specified voltage. bpf c an hold the data only until a defined low level of the backup volta ge (v dr ). user must reset this bit to clear this flag. whe n user resets bpf flag bit, the bit will be updated after t rtcp time. cal calibration mode. when set to 1, a 512 hz squa re wave is output on the int pin. when set to 0, the int pin resumes normal operation. this bit takes priority than sq0/ sq1 and other functions. this bit defaults to 0 ( disabled) on powerup. w write enable: setting the w bit to 1 freezes u pdates of the rtc registers. the user can then writ e to rtc registers, alarm registers, calibration register, interrupt re gister and flags register. setting the w bit to 0 causes the contents of the rtc registers to be transferred to the time kee ping counters if the time has changed. this transfe r process takes t rtcp time to complete. this bit defaults to 0 on power up. r read enable: setting r bit to 1, stops clock u pdates to user rtc registers so that clock updates are not seen during the reading process. set r bit to 0 to resume c lock updates to the holding register. setting this bit does not require w bit to be set to 1. this bit defaults to 0 on powerup. table 12. register map detail (continued) register description [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 31 of 43 best practices nvsram products have been used effectively for over 26 years. while easeofuse is one of the products main syst em values, experience gained working with hundreds of applicat ions has resulted in these suggestions as best practices: the nonvolatile cells in this nvsram product are de livered by cypress with 0x00 written in all cells. incoming in spection routines at customer or contract manufacturers sit es sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end products firmware should not assume an nv array is in a set programmed state. routines that check memory conten t values to determine first time system configuration , cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4byte pattern of 46 e 6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. powerup boot firmware routines should rewrite the nvsram into the desired state (for example, autostore enab led). while the nvsram is shipped in a preset state, best pract ice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertentl y such as program bugs and incoming inspection routines. the v cap value specified in this datasheet includes a minimu m and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this max v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. when base time is updated, these updates are transf erred to the time keeping registers when w bit is set to 0. this transfer takes t rtcp time to complete. it is recommended to initiate software store or hardware store after t rtcp time to save the base time into nonvolatile memory. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 32 of 43 maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. these user guidelines are not tested. storage temperature ............................... . C65 c to +150 c maximum accumulated storage time at 150 c ambient temperature ....................... 1000 h at 85 c ambient temperature ..................... 20 years ambient temperature with power applied ...................................... ..... C55 c to +150 c supply voltage on v cc relative to v ss cy14c064pa: v cc = 2.4 v to 2.6 v ..C0.5 v to +3.1 v cy14b064pa: v cc = 2.7 v to 3.6 v ..C0.5 v to +4.1 v cy14e064pa: v cc = 4.5 v to 5.5 v ..C0.5 v to +7.0 v dc voltage applied to outputs in high z state .................................... . C0.5 v to v cc + 0.5 v input voltage ...................................... .. C0.5 v to v cc + 0.5 v transient voltage (<20 ns) on any pin to ground potential .................. C2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) .......................................... ........ 1.0 w surface mount lead soldering temperature (3 seconds) ............................ .............. +260 c dc output current (1 output at a time, 1s duration) ..... 15 ma static discharge voltage........................... ............... > 2001 v (per milstd883, method 3015) latchup current ................................... ................. > 140 ma table 13. operating range device range ambient temperature v cc cy14c064pa industrial C40 c to +85 c 2.4 v to 2.6 v cy14b064pa 2.7 v to 3.6 v cy14e064pa 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [6] max unit v cc power supply cy14c064pa 2.4 2.5 2.6 v cy14b064pa 2.7 3.0 3.6 v cy14e064pa 4.5 5.0 5.5 v i cc1 average v cc current f sck = 40 mhz; values obtained without output loads (i out = 0 ma) cy14c064pa C C 3 ma cy14b064pa cy14e064pa C C 4 ma f sck = 104 mhz; values obtained without output loads (i out = 0 ma) C C 10 ma i cc2 average v cc current during store all inputs dont care, v cc = max average current for duration t store C C 2 ma i cc3 average v cc current f sck = 1 mhz; v cc = v cc (typ), 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma) C C 1 ma i cc4 average v cap current during autostore cycle all inputs don't care. average current for duration t store C C 3 ma i sb v cc standby current cs > (v cc C 0.2 v). v in < 0.2 v or > (v cc C 0.2 v). w bit set to 0. standby current level after nonvola tile cycle is complete. inputs are static. f sck = 0 mhz. C C 250 a i zz sleep mode current t sleep time after sleep instruction is registered. all inputs are static and configured at cmos logic leve l. C C 8 a i ix [7] input leakage current (except hsb ) C1 C +1 a input leakage current (for hsb ) C100 C +1 a i oz off state output leakage current C1 C +1 a notes 6. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 7. the hsb pin has i out = 2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 33 of 43 v ih input high voltage cy14c064pa 1.7 C v cc + 0.5 v cy14b064pa 2.0 C v cc + 0.5 v cy14e064pa v il input low voltage cy14c064pa v ss C 0.5 C 0.7 v cy14b064pa v ss C 0.5 C 0.8 v cy14e064pa v oh output high voltage i out = C1 ma cy14c064pa 2.0 C C v i out = C2 ma cy14b064pa 2.4 C C v cy14e064pa v ol output low voltage i out = 2 ma cy14c064pa C C 0.4 v i out = 4 ma cy14b064pa C C 0.4 v cy14e064pa v cap storage capacitor between v cap pin and v ss cy14c064pa 170 220 270 f cy14b064pa 42 47 180 f cy14e064pa data retention and endurance parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc (typ) 7 pf c out output pin capacitance 7 pf thermal resistance parameter [8] description test conditions 16-pin soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 56.68 c/w jc thermal resistance (junction to case) 32.11 c/w dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [6] max unit note 8. these parameters are guaranteed by design and are not tested. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 34 of 43 figure 33. ac test loads and waveforms for 2.5 v (cy14c064pa): for 3 v (cy14b064pa): for 5 v (cy14e064pa): ac test conditions description cy14c064pa cy14b064pa cy14e064pa input pulse levels 0 v to 2.5 v 0 v to 3 v 0 v to 3 v input rise and fall times (10% 90%) < 3 ns < 3 ns < 3 ns input and output timing reference levels 1.25 v 1.5 v 1.5 v 2.5 v output 5 pf r1 r2 1290 2.5 v output 30 pf r1 r2 1290 909 909 for tristate specs 3.0 v output 5 pf r1 r2 789 3.0 v output 30 pf r1 r2 789 577 577 for tristate specs 5.0 v output 5 pf r1 r2 512 5.0 v output 30 pf r1 r2 512 963 963 for tristate specs [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 35 of 43 rtc characteristics parameters description min typ [9] max units v rtcbat rtc battery pin voltage 1.8 3.0 3.6 v i bak [10] rtc backup current C 0.45 0.6 a v rtccap [11] rtc capacitor pin voltage 1.6 C 3.6 v tocs rtc oscillator time to start C 1 2 sec v bakfail backup failure threshold 1.8 C 2 v v dr bpf flag retention voltage 1.6 C C v t rtcp rtc processing time from end of w bit set to 0 C C 1 ms r bkchg rtc backup capacitor charge current limiting resist or 350 C 850 ac switching characteristics cypress parameter alt. parameter description 25 mhz (rdrtc instruction) [12] 40 mhz 104 mhz unit min max min max min max f sck f sck clock frequency, sck C 25 C 40 C 104 mhz t cl [13] t wl clock pulse width low 18 C 11 C 4.5 C ns t ch [13] t wh clock pulse width high 18 C 11 C 4.5 C ns t cs t ce cs high time 20 C 20 C 20 C ns t css t ces cs setup time 10 C 10 C 5 C ns t csh t ceh cs hold time 10 C 10 C 5 C ns t sd t su data in setup time 5 C 5 C 4 C ns t hd t h data in hold time 5 C 5 C 3 C ns t hh t hd hold hold time 5 C 5 C 3 C ns t sh t cd hold setup time 5 C 5 C 3 C ns t co t v output valid C 15 C 9 C 8 ns t hhz [13] t hz hold to output highz C 15 C 15 C 8 ns t hlz [13] t lz hold to output lowz C 15 C 15 C 8 ns t oh t ho output hold time 0 C 0 0 C ns t hzcs [13] t dis output disable time C 25 C 20 C 8 ns notes 9. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 10. current drawn from either v rtccap or v rtcbat when v cc < v switch. 11. if v rtccap > 0.5 v or if no capacitor is connected to v rtccap pin, the oscillator will start in tocs time. if a backup capacitor is connected and v rtccap < 0.5 v, the capacitor must be allowed to charge to 0.5 v for os cillator to start. 12. applicable for rtc opcode cycles, address cycles and data out cycles. 13. these parameters are guaranteed by design and ar e not tested. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 36 of 43 figure 34. synchronous data timing (mode 0) figure 35. hold timing hi-z valid in hi-z cssck si so t cl t ch t css t sd t hd t co t oh t cs t csh t hzcs ~ ~ cs sckhold so t sh t hhz t hlz t hh t sh t hh ~ ~ ~ ~ [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 37 of 43 autostore or power-up recall parameter description cy14x064pa unit min max t fa [14] powerup recall duration cy14c064pa C 40 ms cy14b064pa C 20 ms cy14e064pa C 20 ms t store [15] store cycle duration C 8 ms t delay [16] time allowed to complete sram write cycle C 25 ns v switch low voltage trigger level cy14c064pa C 2.35 v cy14b064pa C 2.65 v cy14e064pa C 4.40 v t vccrise [17] v cc rise time 150 C s v hdis [17] hsb output disable voltage C 1.9 v t lzhsb [17] hsb high to nvsram active time C 5 s t hhhd [17] hsb high active time C 500 ns t wake time for nvsram to wake up from sleep mode cy14c064p a C 40 ms cy14b064pa C 20 ms cy14e064pa C 20 ms t sleep time to enter into sleep mode after issuing sleep i nstruction C 8 ms t sb time to enter into standby mode after cs going high C 100 s switching waveforms figure 36. autostore or power-up recall [18] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t fa t fa hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 18 18 15 15 notes 14. t fa starts from the time v cc rises above v switch. 15. if an sram write has not taken place since the l ast nonvolatile cycle, no autostore or hardware sto re takes place. 16. on a hardware store and autostore initiation, sr am write operation continues to be enabled for time t delay . 17. these parameters are guaranteed by design and ar e not tested. 18. read and write cycles are ignored during store, recall, and while v cc is below v switch. 19. during powerup and powerdown, hsb glitches when hsb pin is pulled up through an external resistor. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 38 of 43 software controlled store/recall cycles parameter description cy14x064pa unit min max t recall recall duration C 600 s t ss [20, 21] soft sequence processing time C 500 s figure 37. software store cycle [21] figure 38. software recall cycle [21] figure 39. autostore enable cycle figure 40. autos tore disable cycle 0 0 1 1 1 1 0 0 cs scksi rwi hi-z 0 1 2 3 4 5 6 7 rdy t store 0 1 1 0 0 0 0 0 cs scksi 0 1 2 3 4 5 6 7 rwi hi-z rdy t recall 0 1 0 1 1 0 0 1 cs scksi 0 1 2 3 4 5 6 7 rwi hi-z rdy t ss 0 0 0 1 1 0 0 1 scksi 0 1 2 3 4 5 6 7 rwi hi-z rdy cs t ss notes 20. this is the amount of time it takes to take acti on on a soft sequence command. vcc power must remai n high to effectively register command. 21. commands such as store and recall lock out i/o u ntil operation is complete which further increases this time. see the specific command. [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 39 of 43 figure 41. hardware store cycle [22] hardware store cycle parameter description cy14x064pa unit min max t phsb hardware store pulse width 15 C ns note 22. if an sram write has not taken place since the l ast nonvolatile cycle, no autostore or hardware sto re takes place. ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set ~ ~ ~ ~ ~ ~ [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 40 of 43 ordering code definitions ordering information ordering code package diagram package type operating range cy14b064pasfxit 5185022 16pin soic, 40 mhz industri al cy14b064pasfxi all the above parts are pbfree. option: t tape and reel blank std. p serial (spi) nvsram with rtc density: 064 64 kb cypress cy 14 b 064 p a - 104 sf x i t 14 nvsram package: sf 16pin soic temperature: i industrial (40 to 85 c) die revision: blank no rev a 1 st rev voltage: c 2.5 v b 3.0 v e 5.0 v pbfree frequency: blank 40 mhz 104 104 mhz [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 41 of 43 package diagram figure 42. 16-pin (300 mil) soic (51-85022) 5185022 *c [+] feedback
cy14c064pa cy14b064pa cy14e064pa document #: 00168249 rev. *a page 42 of 43 acronyms document conventions units of measure acronym description bcd binary coded decimal cmos complementary metal oxide semiconductor crc cyclic redundancy check cpha clock phase cpol clock polarity eeprom electrically erasable programmable readonly memory eia electronic industries alliance i/o input/output jedec joint electron devices engineering council nvsram nonvolatile static random access memory rohs restriction of hazardous substances rwi read and write inhibited soic small outline integrated circuit sonos siliconoxidenitrideoxidesilicon spi serial peripheral interface symbol unit of measure c degree celsius hz hertz kbit 1024 bits khz kilo hertz k kilo ohms a micro amperes ma milli amperes f micro farad mhz mega hertz s micro seconds ms milli seconds ns nano seconds pf pico farad v volts ohms w watts [+] feedback
document #: 00168249 rev. *a revised may 6, 2011 pa ge 43 of 43 all products and company names mentioned in this do cument may be the trademarks of their respective ho lders. cy14c064pa cy14b064pa cy14e064pa ? cypress semiconductor corporation, 2011. the info rmation contained herein is subject to change witho ut notice. cypress semiconductor corporation assume s no responsibility for the use of any circuitry other than circuitry embodied in a cypres s product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safe ty applications, unless pursuant to an express writ ten agreement with cypress. furthermore, cypress do es not authorize its products for use as critical components in lifesupport systems where a malfunct ion or failure may reasonably be expected to result in significant injury to the user. the inclusion o f cypress products in lifesupport systems application implies that the manufacturer assumes a ll risk of such use and in doing so indemnifies cyp ress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subject to worldwide patent pr otection (united states and foreign), united states copyright laws and international trea ty provisions. cypress hereby grants to licensee a personal, nonexclusive, nontransferable license t o copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom softw are and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable a greement. any reproduction, modification, translati on, compilation, or representation of this source c ode except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, i ncluding, but not limited to, the implied warrantie s of merchantability and fitness for a particular pur pose. cypress reserves the right to make changes wi thout further notice to the materials described her ein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the i nclusion of cypress product in a lifesupport syst ems application implies that the manufacturer assumes all risk of such use and in doing so indemn ifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, s olution centers, manufacturers representatives, an d distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy14c064pa, cy14b064pa, cy14e064pa, 64-kbit (8 k 8) spi nvsram with real time clock document number: 001-68249 rev. ecn no. submission date orig. of change description of change ** 3202424 03/22/2011 gvch new datasheet *a 3248510 05/04/2011 gvch datasheet status changed fro m preliminary to final [+] feedback

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